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https://github.com/vosen/ZLUDA.git
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867e4728d5
* LLVM unit tests: add assembly files * LLVM unit tests: first attempt * LLVM unit tests: fix - parse bitcode in context * LLVM unit tests: use pretty_assertions for line-by-line diff * LLVM unit tests: Write IR to file for failed test * LLVM unit tests: just use the stack * LLVM unit tests: use MaybeUninit * LLVM unit tests: add mul24.ll * LLVM unit tests: Adjustments after review * LLVM unit tests: Include emit_llvm::Context in emit_llvm::Module * LLVM unit tests: Fix typo * LLVM unit tests: Context need not be pub
40 lines
1.5 KiB
LLVM
40 lines
1.5 KiB
LLVM
declare i32 @__zluda_ptx_impl_sreg_tid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_ntid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_ctaid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_nctaid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_clock() #0
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declare i32 @__zluda_ptx_impl_sreg_lanemask_lt() #0
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define amdgpu_kernel void @vector4(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
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%"38" = alloca i64, align 8, addrspace(5)
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%"39" = alloca i64, align 8, addrspace(5)
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%"40" = alloca <4 x i32>, align 16, addrspace(5)
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%"41" = alloca i32, align 4, addrspace(5)
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br label %1
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1: ; preds = %0
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%"42" = load i64, ptr addrspace(4) %"36", align 4
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store i64 %"42", ptr addrspace(5) %"38", align 4
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%"43" = load i64, ptr addrspace(4) %"37", align 4
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store i64 %"43", ptr addrspace(5) %"39", align 4
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%"45" = load i64, ptr addrspace(5) %"38", align 4
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%"50" = inttoptr i64 %"45" to ptr
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%"44" = load <4 x i32>, ptr %"50", align 16
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store <4 x i32> %"44", ptr addrspace(5) %"40", align 16
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%"46" = load <4 x i32>, ptr addrspace(5) %"40", align 16
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%"29" = extractelement <4 x i32> %"46", i8 3
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store i32 %"29", ptr addrspace(5) %"41", align 4
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%"48" = load i64, ptr addrspace(5) %"39", align 4
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%"49" = load i32, ptr addrspace(5) %"41", align 4
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%"53" = inttoptr i64 %"48" to ptr
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store i32 %"49", ptr %"53", align 4
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ret void
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}
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attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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