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https://github.com/vosen/ZLUDA.git
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867e4728d5
* LLVM unit tests: add assembly files * LLVM unit tests: first attempt * LLVM unit tests: fix - parse bitcode in context * LLVM unit tests: use pretty_assertions for line-by-line diff * LLVM unit tests: Write IR to file for failed test * LLVM unit tests: just use the stack * LLVM unit tests: use MaybeUninit * LLVM unit tests: add mul24.ll * LLVM unit tests: Adjustments after review * LLVM unit tests: Include emit_llvm::Context in emit_llvm::Module * LLVM unit tests: Fix typo * LLVM unit tests: Context need not be pub
64 lines
2.4 KiB
LLVM
64 lines
2.4 KiB
LLVM
declare i32 @__zluda_ptx_impl_sreg_tid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_ntid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_ctaid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_nctaid(i8) #0
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declare i32 @__zluda_ptx_impl_sreg_clock() #0
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declare i32 @__zluda_ptx_impl_sreg_lanemask_lt() #0
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define amdgpu_kernel void @setp(ptr addrspace(4) byref(i64) %"45", ptr addrspace(4) byref(i64) %"46") #0 {
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%"47" = alloca i64, align 8, addrspace(5)
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%"48" = alloca i64, align 8, addrspace(5)
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%"49" = alloca i64, align 8, addrspace(5)
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%"50" = alloca i64, align 8, addrspace(5)
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%"51" = alloca i64, align 8, addrspace(5)
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%"52" = alloca i1, align 1, addrspace(5)
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br label %1
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1: ; preds = %0
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%"53" = load i64, ptr addrspace(4) %"45", align 4
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store i64 %"53", ptr addrspace(5) %"47", align 4
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%"54" = load i64, ptr addrspace(4) %"46", align 4
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store i64 %"54", ptr addrspace(5) %"48", align 4
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%"56" = load i64, ptr addrspace(5) %"47", align 4
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%"68" = inttoptr i64 %"56" to ptr
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%"55" = load i64, ptr %"68", align 4
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store i64 %"55", ptr addrspace(5) %"49", align 4
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%"57" = load i64, ptr addrspace(5) %"47", align 4
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%"69" = inttoptr i64 %"57" to ptr
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%"36" = getelementptr inbounds i8, ptr %"69", i64 8
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%"58" = load i64, ptr %"36", align 4
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store i64 %"58", ptr addrspace(5) %"50", align 4
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%"60" = load i64, ptr addrspace(5) %"49", align 4
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%"61" = load i64, ptr addrspace(5) %"50", align 4
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%"59" = icmp ult i64 %"60", %"61"
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store i1 %"59", ptr addrspace(5) %"52", align 1
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%"62" = load i1, ptr addrspace(5) %"52", align 1
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br i1 %"62", label %"15", label %"16"
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"15": ; preds = %1
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store i64 1, ptr addrspace(5) %"51", align 4
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br label %"16"
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"16": ; preds = %"15", %1
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%"64" = load i1, ptr addrspace(5) %"52", align 1
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br i1 %"64", label %"18", label %"17"
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"17": ; preds = %"16"
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store i64 2, ptr addrspace(5) %"51", align 4
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br label %"18"
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"18": ; preds = %"17", %"16"
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%"66" = load i64, ptr addrspace(5) %"48", align 4
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%"67" = load i64, ptr addrspace(5) %"51", align 4
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%"70" = inttoptr i64 %"66" to ptr
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store i64 %"67", ptr %"70", align 4
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ret void
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}
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attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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